Multi-level hierarchical scheduling in ethernet switches

The complexity of Networked Embedded Systems (NES) has been growing steeply, due to increases both in size and functionality, and is becoming a major development concern. This situation is pushing for paradigm changes in NES design methodologies towards higher composability and flexibility. Component-oriented design technologies, in particular supported by server-based scheduling, seem to be good candidates to provide the needed properties. As a response we developed a multi-level hierarchical serverbased architecture for Ethernet switches that provides composability and supports online adaptation and reconfiguration. This paper extends our work, presenting the associated response-time based schedulability analysis, necessary for the admission control procedure. Additionally, we have derived the temporal complexity of the analysis, which is shown to be O(n2), where n is the number of higher priority components associated with a given server. Finally, we present a proof-of-concept implementation and a set of experimental results that validates the analysis. Copyright © 2011 ACM.
Sponsors: IEEE Council on Electronic Design Automation (CEDA); IEEE Circuits and Systems Society; IEEE Computer Society; ACM SIGMICRO; Special Interest Group on Embedded Systems (ACM SIGBED); Special Interest Group on Design Automation (ACM SIGDA)