Algorithm for the choice of topology in reconfigurable networks with real-time support

Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks, and to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this report, we describe an algorithm for the choice of topology in, e.g., packet-switched on-chip networks, considering the real-time demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about the traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures. Although we have targeted for reconfigurable Network-on-Chip architectures, the algorithm can also be used for other systems. Our algorithm gives the opportunity for topology choice at design stage, both for static network topologies and for reconfigurable network topologies that can be reconfigured during run-time.