A multithreading RISC-V implementation for Lagarto Architecture

The development of computer architecture standards for many years was mainly delegated to a few groups of companies that define most of the popular Instructions Set Architectures (ISAs). While the Information Technologies field is constructed through many efforts of interfaces resulting in abstraction layers at several levels, the interaction between software and hardware that an ISA define has particular importance in the field. RISC-V emerges as a potential instrument that unbound the limitations of privates standards and committing to the goal of developing a sustainable model capable of supplying the actual needs of the computation requirements of our society for a broad set of technological end-nodes. This work comprehends the design and implementation of a multithreading RISC-V core based in the Lagarto 1 processor architecture and embedded in the preDRAC SoC inheriting the multicore capabilities of it; looking to contribute to the open-source hardware initiative.