Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation

This thesis aims to evaluate MathWorks HDL (Hardware Descriptive Language) Coder and compare the results with designs produced by its vendor dependent counterparts. The focus is mainly on evaluate the design effort needed to close timing and to get optimal resource mapping for a selected design. Different tests were carried out with the designs made in HDL Coder ranging from a small design to a complex digital front end design. Several logic tests were also carried out to understand the efficiency of the hardware produced from HDL Coder. To get our hands on with the tool, a power meter was undertaken as the design under test. Further, a down sampling filter chain was designed in HDL Coder and lastly, a branched filter was designed. Results have been presented for the unoptimized design and the various optimizations tried. An analysis of the different methodologies used is discussed and how the tool can make the design flow more effective. With the time invested in learning and using the tool, an experience of HDL Coder as a HLS (High Level Synthesis)) tool can be analyzed and compared to other HLS tools. In conclusion, it was found out that in the bigger designs HDL Coder did not have a problem meeting the timing requirements for the selected designs and the results are comparable. However, it does not map optimally to the resources on the FPGA (Field Programmable Gate Array) fabric and it was difficult to change the mapping of resources according to constraints. On analysis, the HDL Coder blocks consume a lot of DSP (Digital Signal Processing) slices compared to the vendor dependent counterparts. Though, the tool is faster and easier to learn, work with and many optimization methods can be done automatically by the tool. Additionally, there is no need to run synthesis on a separate vendor cause this can be done by HDL Coder which improves the workflow. Using HDL Coder in a design methodology would increase productivity because of it being vendor independent. Wherea
The number of transistors on a silicon chip has doubled every two years as per Moore's law and the design requirements have been exponentially increasing. Wireless systems are also getting more and more complex. With the development of 5G, this has been no exception. %To meet these ever increasing requirements, results in sophisticated hardware implementations. This complexity increases the design workload which makes the design flow multiple times longer and puts a lot of pressure on the designer. These complex systems generally contain a mix of DSP algorithms such as FFT's, IIR filters, FIR poly-phase filters. With the advancements in the FPGA technology, designs can be built on them with great flexibility. Since the time to market is critical, the development time window is reducing drastically. This is where High-Level Synthesis (HLS) and Model-Based Design (MBD) tools fit in. MBD is a methodology which lets the designer creates models of the design implementation and promotes the use of the high level synthesis within it to create RTL relatively easily. HLS tools have been designed to automate and accelerate design by moving manual work on to a higher level. FPGA vendors have come out with high level tools (HLT) optimized specifically for their hardware and are integrated within the MBD tool Simulink. These tools are vendor specific and the learning curve can be quite steep and a deeper understanding of hardware is needed to use them. One of the problems with this vendor specific approach arises if the same design needs to be ported on to different FPGA vendor platform. This causes the same design to be replicated and re-implemented in the other vendor specific HLT. This procedure is time consuming and requires knowledge of the new tool. One other tool which looks promising and produces vendor independent synthesizable HDL code is HDL Coder provided by MathWorks. In this thesis, Simulink is the MBD tool used along with the HLTs like HDL Coder, Xilinx SysGen and