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From FPGA to ASIC: A RISC-V processor experience
- Publication Year :
- 2019
-
Abstract
- This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC.
Details
- Database :
- OAIster
- Notes :
- application/pdf, English
- Publication Type :
- Electronic Resource
- Accession number :
- edsoai.on1141699013
- Document Type :
- Electronic Resource