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WCET-aware compilation techniques for clustered VLIW processors

Authors :
Hui, Wu, Computer Science & Engineering, Faculty of Engineering, UNSW
Su, Xuesong, Computer Science & Engineering, Faculty of Engineering, UNSW
Hui, Wu, Computer Science & Engineering, Faculty of Engineering, UNSW
Su, Xuesong, Computer Science & Engineering, Faculty of Engineering, UNSW
Publication Year :
2018

Abstract

In real-time systems, it is crucial to guarantee that all the timing constraints are met at design stage. The WCET of each task has a significant impact on finding a feasible schedule for a set of real-time tasks. If we can reduce the WCET of each program, we are more likely to find a feasible schedule. Therefore, it is important to minimize the WCET of each program. An optimizing compiler plays a key role in reducing the WCET of a program. In this thesis, we investigate three important problems of reducing the WCET of a program executed on clustered VLIW processors, and propose novel, efficient approaches.Firstly, we investigate the problem of reducing the number of branch mispredictions for a program such that its WCET is minimized, and propose a novel branch correlation-based, hybrid branch prediction heuristic approach. Our approach consists of a static profile-based branch correlation analyzer and a dynamic branch predictor. The static profile-based branch correlation analyzer uses profiling and data dependency analysis to find precise correlations between branches of a program and identifies all the branches that do not have any impact on the WCET of the program. The dynamic predictor uses the correlation information to make online predictions. We have implemented our approach and compared it with the two state-of-the-art branch prediction approaches by using a set of benchmark suites. The experimental results show that our approach outperforms the two state-of-the-art approaches.Secondly, we investigate the problem of instruction scheduling and register allocation for a program executed on a clustered VLIW processor such that the WCET of the program is minimized, and propose a novel, unified instruction scheduling and register allocation heuristic approach. Our approach iteratively selects a set of basic blocks that may have impact on the WCET found by using WCET-aware graph reduction, performs live range splitting for a set of selected variables in those bas

Details

Database :
OAIster
Notes :
English
Publication Type :
Electronic Resource
Accession number :
edsoai.on1100990323
Document Type :
Electronic Resource