Implementation of the configurable fault tolerant system experiment on NPSAT-1

Space is a harsh environment, full of high-energy radiation that can cause single-event effects (SEE) in orbiting satellites. Some of these effects, such as single-event upsets and single-event functional interrupts, occur when ionizing radiation causes the logical value in a memory element to change and are detectable and correctable through various error mitigation techniques. In this thesis, we develop and implement a hardware solution to combat these SEE for deployment as an experimental module on Naval Postgraduate School Satellite 1 (NPSAT-1). Based on the relatively benign orbit of NPSAT-1, industrial-grade, commercial-off-the-shelf components that have shown tolerance to radiation were selected to keep costs low. The primary source of mitigation relies on a globally triple-modular redundant microprocessor system instantiated inside of a XILINX Kintex-7 field-programmable gate array. The system consists of an open-source microprocessor without interlocked pipeline stages (MIPS) based processor softcore, a cached memory structure capable of accessing double-data rate type three and secure digital card memories, an interface to the main satellite bus, and XILINX’s soft error mitigation softcore. The hardware was tested both in and out of the system and verified to work on the ground with faults injected. Other techniques to mitigate errors due to SEE, such as memory scrubbing, are intended to be added before launch.
http://archive.org/details/implementationof1094548536
Lieutenant, United States Navy
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