Hardware Supported Multi-Core Communications for Efficient Parallel Discrete Event Simulation

With the present and future proliferation of multi-core architecture computing devices, we expect that parallel programming and PDES in particular, will become more prevalent. In research presented here, we explored ways to dramatically reduce the overhead described above for PDES applications by designing and testing specialized hardware that could be incorporated into multi- core architecture designs. Once this hardware is incorporated into multi-core architectures, the overhead and message passing will be reduced to near zero, independent of the number of cores in the architecture.
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