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PROTEUS: A High-Performance Parallel-Architecture Simulator

Authors :
MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
Brewer, Eric A.
Dellarocas, Chrysanthos N.
Colbrook, Adrian
Weihl, William E.
MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
Brewer, Eric A.
Dellarocas, Chrysanthos N.
Colbrook, Adrian
Weihl, William E.
Source :
DTIC AND NTIS
Publication Year :
1991

Abstract

PROTEUS is a high-performance simulator for MIMD multiprocessors. It is fast, accurate, and flexible: it is one to two orders of magnitude faster than comparable simulators, it can reproduce results from real multiprocessors, and it is easily configured to simulate a wide range of architectures. PROTEUS provides a modular structure that simplifies customization and independent replacement of parts of architecture. There are typically multiple implementations of each module that provide different combinations of accuracy and performance; users pay for accuracy only when and where they need it. Finally, PROTEUS provides repeatability, nonintrusive monitoring and debugging, and integrated graphical output, which result in a development environment superior to those available on real multiprocessors.

Details

Database :
OAIster
Journal :
DTIC AND NTIS
Notes :
text/html, English
Publication Type :
Electronic Resource
Accession number :
edsoai.ocn832037737
Document Type :
Electronic Resource