Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

Interest is growing in the use of FPGA devices for high-performance, efficient parallel computation. The large amount of programmable logic, internal routing, and memory can be used to perform a wide variety of high-performance computation more efficiently than traditional microprocessor-based computing architectures. The productivity of FPGA design, however, is very low. FPGA design is very time consuming and requires low-level hardware design skills. This study investigated this FPGA design productivity problem and identified potential solutions that will provide revolutionary improvements in design productivity. Three research areas that must be addressed to achieve such improvements are significant improvement in reuse of FPGA circuits, identification and deployment of higher level design abstractions, and increasing the number of turns per day to significantly increase the number of design iterations. The results of this study suggest that with adequate advancement in each of these areas, FPGA design productivity can be increased by 25X over current practice.
Prepared in cooperation with Virginia Polytechnic Institute and State Univ., Blacksburg, VA. Sponsored in part by DARPA.