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High yielding self-aligned contact process for a 0.150-[micro]m, DRAM technology

Authors :
Rupp, Thomas S.
Dobuzinsky, David
Lu, Zhijian
Sardesai, Viraj Y.
Liu, Hang-Yip
Maldei, Michael
Faltermeier, John
Gambino, Jeff
Source :
IEEE Transactions on Semiconductor Manufacturing. May, 2002, Vol. 15 Issue 2, p223, 6 p.
Publication Year :
2002

Abstract

This paper describes improvements in the self-aligned contact process for 0.150 [micro]m and 0.175 [micro]m technology generations. Using a dynamic random access memory cell layout, we show that self-aligned contacts can be formed at 0.175 [micro]m ground rules and beyond by using a [C.sub.4.][F.sub.8]-C[H.sub.2][F.sub.2] chemistry. With the improved etch selectivity, gate cap nitride thickness can be reduced, resulting in a smaller aspect ratio for the gate etch, borophosphosilicate glass fill, and contact etch. With a rectangular contact, the area can be increased and the process windows for lithography and etch are improved. The process window for lithography increases by up to 40%, the aspect ratio for the etch and the contact fill is less, and the sensitivity to misalignment is reduced. The combination of rectangular contacts and [C.sub.4][F.sub.8]-C[H.sub.2][F.sub.2] chemistry greatly enhances the product yield. Index Terms--0.15-[micro]m technology, borderless contact, contact shape, DRAM, etch stop, reactive ion etching (RIE), selective etching, self-aligned contact (SAC).

Details

ISSN :
08946507
Volume :
15
Issue :
2
Database :
Gale General OneFile
Journal :
IEEE Transactions on Semiconductor Manufacturing
Publication Type :
Academic Journal
Accession number :
edsgcl.86869090