A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.compeleceng.2008.11.019 Byline: Ling Wang (a), Hui Song (a), Yingtao Jiang (b), Lihong Zhang (c) Keywords: Interconnect; Mesh; Routing; Network-on-chip; SoC Abstract: In this paper, we present a routing algorithm that combines the shortest path routing and adaptive routing schemes for NoCs. In specific, routing follows the shortest path to ensure low latency and low energy consumption. This routing scheme requires routing information be stored in a series of routing tables created at the routers along the routing path from the source to the destination. To reduce the exploration space and timing cost for selecting the routing path, a routing list and routing table for each node are created off-line. Routing table is updated on-line to reflect the dynamic change of the network status to avoid network congestion. To alleviate the high hardware implementation cost associated with the routing tables, a method to help reduce the size of the routing tables is also introduced. Compared to the existing routing algorithms, the experimental results have confirmed that the proposed algorithm has better performance in terms of routing latency and power consumption. Author Affiliation: (a) Department of Computer Science and Technology, Harbin Institute of Technology, #715, Harbin 150001, PR China (b) Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, USA (c) Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, Canada