Reduction of RIE-damage by N20-anneal of thermal gate oxide

We have investigated RIE-induced damage in MOS devices with thermal oxide as well as [N.sub.2]O-annealed oxide as gate dielectrics. A systematic improvement in robustness against RIE-induced damage is seen when [N.sub.2]O flow rate and/or [N.sub.2]O anneal temperature are increased. We have demonstrated a [N.sub.2]O anneal process at 900 [degrees] C, which provides a robust Si[O.sub.2]/Si interface against plasma damage and hot carrier stress.