Experimental verification of scan-architecture-based evaluation technique of SET and SEU soft-error rates at each flip-flop in logic VLSI systems

Authors :: Yanagawa, Y.
Kobayashi, D.
Hirose, K.
Makino, T.
Saito, H.
Ikeda, H.
Onoda, S.
Hirao, T.
Ohshima, T.
Source :: IEEE Transactions on Nuclear Science. August, 2009, Vol. 56 Issue 4, p1958, 6 p.
Publication Year :: 2009

Subjects :: Radiation -- Methods
Semiconductor industry -- Methods
Very-large-scale integration -- Methods
Arms control -- Verification
Arms control -- Methods
Semiconductor industry
Business
Electronics
Electronics and electrical industries

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