Memory reduction methodology for distributed-arithmetic-based DWT/IDWT exploiting data symmetry

In this brief, we show that by exploiting the inherent symmetry of the discrete wavelet transform (DWT) algorithm and consequently storing only the nonrepetitlve combinations of filter coefficients, the size of required memory can be significantly reduced. Subsequently, a memory-efficient architecture for DWT/inverse DWT is proposed. It occupies 6.5-[mm.sup.2] silicon area and consumes 46.8-[micro]W power at 1 MHz for 1.2 V using 0.13-[micro]m standard cell technology. Index Terms--Distributed arithmetic (DA), low-power architecture, multiplierless implementation, very large scale integration, wavelet.