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A digitally calibrated CMOS transconductor with a 100-MHz bandwidth and 75-dB SFDR
- Source :
- IEEE Transactions on Circuits and Systems-II-Express Briefs. Nov, 2008, Vol. 55 Issue 11, p1089, 5 p.
- Publication Year :
- 2008
-
Abstract
- This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current--voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-[micro]m CMOS process, the transconductor occupies 220 x 160 [micro][m.sup.2] active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption. Index Terms--High-linearity amplifier, operational transconductance amplifier (OTA), transconductor, voltage-to-current converter.
Details
- Language :
- English
- ISSN :
- 15497747
- Volume :
- 55
- Issue :
- 11
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Circuits and Systems-II-Express Briefs
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.192587658