Configurable multi-rate decoder architecture for QC-LDPC codes based broadband broadcasting system

In this paper we present a Base-matrix based decoder architecture for multi-rate QC-LDPC codes proposed in broadband broadcasting system. We use the Modified Min-Sum Algorithm (MMSA) as the decoding algorithm in this architecture, which lowers the complexity of the LDPC decoder while keeping almost the same performance or even better. Based on this algorithm, we designed a novel check node processing unit to reduce the complexity of the decoder and facilitate the multiplex of the processing units. The decoder designed with hardware constraints is not only scalable in throughput, but also easily configurable to support different QC-LDPC codes flexible in code rate and code length. Index Terms--Base-matrix, broadcast, channel coding, FPGA, MMSA, multi-rate, quasi-cyclic low-density parity-check codes (QC-LDPCC), scalable throughput.