A reconfigurable mixed-signal VLSI implementation of distributed arithmetic used for finite-impulse response filtering

A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate voltage references. The effect of the offset and gain errors on DA computational accuracy is analyzed, and theoretical results for the limitations of this design strategy are presented. This architecture is fabricated in a 0.5-[micro]m CMOS process, and configured as a 16-tap finite impulse response (FIR) filter to demonstrate the reconfigurability and computational efficiency. The measurement results for comb, low-pass, and bandpass filters at 32/50-kHz sampling frequencies are presented. This implementation occupies around 1.125 [mm.sup.2] of die area and consumes 16 mW of static power. The filter order can be increased at the cost of 0.011 [mm.sup.2] of die area and 0.02 mW of power per tap. Index Terms--Array of tunable FG voltage reference (epot), fistributed arithmetic (DA), finite-impulse response (FIR) filter, floating-gate (FG) transistor, post processing.