Application of low temperature scanning electron microscopy for the investigation of single-electron tunneling circuits

Low temperature scanning electron microscopic technique is employed for the spatially resolved investigation of single-electron tunneling (SET) circuits. Signals from various parts of the circuits are imaged with the help of circuit voltage, recording as a function of the beam coordinates. Charge trapping near SET-transistor induces memory effect. The efficiency of this technique is demonstrated with a system having 11 electrons.