An on-sensor bit-serial column-parallel processing architecture for high-speed discrete Fourier transform

This brief presents a discrete Fourier transform (DFT) processor based on a bit-serial column-parallel processing architecture suitable for integrating it on CMOS image sensors. Using a column-parallel A/D converter (ADC) array, column-line sensor outputs of the two-dimensional image array are digitized. The ADC outputs are sliced to one bit and are given to the bit-serial column-parallel DFT processor from the MSB to the LSB. A high-speed and cost-effective implementation can be expected. In the case of 256 x 256-point DFT for 8-b image data, the processing time is estimated to be 2 ms at a clock frequency of 100 MHz, which corresponds to the 500-frames/s real-time processing. Index Terms--CMOS image sensor, discrete Fourier transform (DFT), distributed arithmetic, functional image sensor.