IMD reduction in CMOS double-balanced mixer using multibias dual-gate transistors

This paper presents a novel and simple linearization scheme for a CMOS double-balanced mixer based un the use of multibias dual-gate transistors. In this technique, intermodulation-distortion (IMD) components with proper phase relationship, generated by devices operating at different bias conditions, are combined together to improve the linearity of mixers. For experimental verification, the measured performance of a fabricated CMOS mixer is shown. Over 35 dB of IMD reduction is achieved by the proposed method under proper biasing condition. Index Terms--Double-balanced mixer, dual-gate transistor, linearization.