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Frequency multiply circuit for superconducting A/D converter
- Source :
- IEEE Transactions on Applied Superconductivity. June, 2005, Vol. 15 Issue 2, p431, 4 p.
- Publication Year :
- 2005
-
Abstract
- A new frequency multiply circuit generating a 20 GHz sampling clock from an external 5 GHz signal for a low pass sigma-delta modulator is proposed and designed. The numerical simulations are used to confirm that the period jitter of single flux quantum (SFQ) pulse trains generated by the ladder circuit could be reduced to value small enough to realize 14-bit resolution for 10 MHz bandwidth.
Details
- Language :
- English
- ISSN :
- 10518223
- Volume :
- 15
- Issue :
- 2
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Applied Superconductivity
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.135911458