Highly linear 2.5-V CMOS [SIGMA][DELTA] modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma-delta modulator ([SIGMA][DELTA]M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-[micro]m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 311-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within [+ or -] 0.85 and [+ or -] 0.80 LS[B.sub.14] b, respectively. The [SIGMA][DELTA] modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the [SIGMA][DELTA] modulator. Index Terms--Analog-to-digital converter (ADC), asymmetric digital subscriber line (ADSL), MASH, sigma-delta modulation, switched-capacitor circuits.