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Some conditions under which hierarchical verification is O(N)

Authors :
Scheffer, Louis K.
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. May, 2003, Vol. 22 Issue 5, p643, 4 p.
Publication Year :
2003

Subjects

Subjects :
Circuit designer
Integrated circuit design
Circuit design -- Research

Details

Language :
English
ISSN :
02780070
Volume :
22
Issue :
5
Database :
Gale General OneFile
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publication Type :
Academic Journal
Accession number :
edsgcl.104566450

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