A steady‐state analysis method for pole‐to‐pole faults under different transition resistances in voltage source converter‐based DC systems

Abstract Fault analysis is an essential prerequisite for fault detection, location and isolation. A detailed fault analysis method on the steady state of the pole‐to‐pole fault for voltage source converter (VSC) based DC systems is presented in this paper. According to fault characteristics under different transition resistances (TRs), the steady‐state response is divided into three scenarios: low transition resistance with blocked converter (LTRBC), medium transition resistance with blocked converter (MTRBC) and high transition resistance with unblocked converter (HTRUC). When TR is relatively low, fault currents through insulated gate bipolar transistors (IGBTs) are large and the converter is blocked. After an in‐depth study of freewheel diodes’ conduction states, the iterative method is utilized to solve the steady state under blocked converter. When TR is relatively high, fault currents through IGBTs are not large enough to block the converter. With the unblocked converter, control strategy and pulse width modulation (PWM) are investigated to obtain steady‐state fault currents. Finally, a reasonable simulation model was built in PSCAD/EMTDC software. The simulation results verified the fault analysis accuracy, with much less calculation error than that of the conventional method. Besides, the proposed analysis method was proved applicable to fault scenarios under different TRs.