FPGA implementation of a direct digital frequency synthesizer based on piecewise polynomial approximation

A design of direct digital frequency synthesizer(DDFS) is proposed in this paper.Piecewise polynomial approximation algorithm is used to replace the look-up table,which leads to a phase to cosine amplitude mapper.The polynomial expression chosen by minimum-mead square error is used to achieve the maximum spurious free dynamic range(SFDR)，about 94.98 dBc. A DDFS of 14 bit input phase to amplitude mapper is developed in FPGA and an optimized digital system is designed to implement the method.It is shown that digitized amplitude error is smaller than 2.6×10-4 and promising result of 93 dBc SFDR,which is much closer to theoretical upper bound .This study also provide a new method about scaling signal source for next generation induction magnetometer.