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High-Efficiency High Voltage Hybrid Charge Pump Design With an Improved Chip Area
- Source :
- IEEE Access, Vol 9, Pp 94386-94397 (2021)
- Publication Year :
- 2021
- Publisher :
- IEEE, 2021.
-
Abstract
- A hybrid charge pump was developed in a 0.13- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage.
Details
- Language :
- English
- ISSN :
- 21693536
- Volume :
- 9
- Database :
- Directory of Open Access Journals
- Journal :
- IEEE Access
- Publication Type :
- Academic Journal
- Accession number :
- edsdoj.79f06f20c8eb4f61a7d93909e3bffb15
- Document Type :
- article
- Full Text :
- https://doi.org/10.1109/ACCESS.2021.3091808