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High Performance 128-Channel Acquisition System for Electrophysiological Signals

Authors :
Kasun Sameera Mannatunga
Sawal Hamid Md Ali
Maria Liz Crespo
Andres Cicuttin
Jayathu G. Samarawikrama
Source :
IEEE Access, Vol 8, Pp 122366-122383 (2020)
Publication Year :
2020
Publisher :
IEEE, 2020.

Abstract

The increased popularity of investigations and exploits in the fields of neurological rehabilitation, human emotion recognition, and other relevant brain-computer interfaces demand the need for flexible electrophysiology data acquisition systems. Such systems often require to be multi-modal and multi-channel capable of acquiring and processing several different types of physiological signals simultaneously in realtime. Developments of modular and scalable electrophysiological data acquisition systems for experimental research enhance understanding and progress in the field. To contribute to such an endeavor, we present an open-source hardware project called High-Channel Count Electrophysiology or HiCCE, targeting to produce an easily-adaptable, cost-effective, and affordable electrophysiological acquisition system as an alternative solution for mostly available commercial tools and the current state of the art in the field. In this paper, we describe the design and validation of the entire chain of the HiCCE-128 electrophysiological data acquisition system. The system comprises of 128 independent channels capable of acquiring signal at 31.25 kHz, with 16 effective bits per channel with a measured noise level of about 3 μV. The reliability and feasibility of the implemented system have been confirmed through a series of tests and real-world applications. The modular design methodology based on the FPGA Mezzanine Card (FMC) standard allows the connection of the HiCCE-128 board to programmable system-on-chip carrier devices through the high-speed FMC link. The implemented architecture enables end users to add various high-response electrophysiological signal processing techniques in the field programmable gate arrays (FPGA) part of the system on chip (SoC) device on each channel in parallel according to application specification.

Details

Language :
English
ISSN :
21693536
Volume :
8
Database :
Directory of Open Access Journals
Journal :
IEEE Access
Publication Type :
Academic Journal
Accession number :
edsdoj.685d6657daea4e1fb521440db0fcb969
Document Type :
article
Full Text :
https://doi.org/10.1109/ACCESS.2020.3007082