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Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer
- Source :
- Nanoscale Research Letters, Vol 14, Iss 1, Pp 1-7 (2019)
- Publication Year :
- 2019
- Publisher :
- SpringerOpen, 2019.
-
Abstract
- Abstract An ultra-low specific on-resistance (R on,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that R on,sp is 8.5 mΩ·mm2 while BV is 43 V.
Details
- Language :
- English
- ISSN :
- 19317573 and 1556276X
- Volume :
- 14
- Issue :
- 1
- Database :
- Directory of Open Access Journals
- Journal :
- Nanoscale Research Letters
- Publication Type :
- Academic Journal
- Accession number :
- edsdoj.3fc4c600659b4c3e81af0b6d06c49335
- Document Type :
- article
- Full Text :
- https://doi.org/10.1186/s11671-019-2866-5