Novel methodology to determine leakage power in standard cell library design

In the most advanced technology nodes, leakage has become a major concern for integrated circuits designers. In addition, the leakage calculation using SPICE simulations takes a large amount of time for the entire library of standard cells for the different PVT (Process, Voltage, and Temperature) conditions. However IC Designers usually need a fast access to the leakage current estimation in order to validate their designs. In this context, the present paper proposes a new approach of the leakage estimation. The aim of this methodology is to predict the leakage of a standard cell accurately and in a short amount of time. This method is applied to all the cells of the used standard cell library and is based on mathematical models developed from the leakage physical equation. The results of the leakage calculated with this technique shows an average error of 5%. The context of this work is part of a fast generation of a full liberty file of a standard cell library using the curve fitting method.