A hardware track-trigger for CMS at the High Luminosity LHC

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) is designed to study a wide range of high energy physics phenomena. It employs a large all-silicon tracker within a 3.8 T magnetic solenoid, which allows precise measurements of transverse momentum (pT) and vertex position. This tracking detector will be upgraded to coincide with the installation of the High-Luminosity LHC, which will provide up to about 10^35 / cm^2 / s to CMS, or 200 collisions per 25 ns bunch crossing. This new tracker must maintain the nominal physics performance in this more challenging environment. Novel tracking modules that utilise closely spaced silicon sensors to discriminate on track pT have been developed that would allow the readout of only hits compatible with pT > 2−3 GeV tracks to off-detector trigger electronics. This would allow the use of tracking information at the Level-1 trigger of the experiment, a requirement to keep the Level-1 triggering rate below the 750 kHz target, while maintaining physics sensitivity. This thesis presents a concept for an all Field Programmable Gate Array (FPGA) based track finder using a fully time-multiplexed architecture. A hardware demonstrator has been assembled to prove the feasibility and capability of such a system. The track finding demonstrator uses a projective binning algorithm called a Hough Transform to form track-candidates, which are then cleaned and fitted by a combinatorial Kalman Filter. Both of these algorithms are implemented in FPGA firmware. This demonstrator system, composed of eight Master Processor Virtex-7 (MP7) processing boards, is able to successfully find tracks in one eighth of the tracker solid angle at a time, within the expected 4 μs latency constraint. The performance for a variety of physics scenarios is studied, as well as the proposed scaling of the demonstrator to the final system and new technologies.