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Sub-40mV Sigma-VTH IGZO nFETs in 300mm Fab

Authors :
Mitard, Jerome
Kljucar, Luka
Rassoul, Nouredine
Dekkers, Harold
van Setten, Michiel
Chasin, Adrian Vaisman
Pourtois, Geoffrey
Belmonte, Attilio
Donadio, Gabriele Luca
Goux, Ludovic
Mao, Ming
Puliyalil, Harinarayanan
Teugels, Lieve
Tsvetanova, Diana
Nag, Manoj
Steudel, Soeren
Borniquel, Jose Ignacio del Agua
Ramalingam, Jothilingam
Delhougne, Romain
Wilson, Chris J.
Tokei, Zsolt
Kar, Gouri Sankar
Source :
ECS Trans. 98 205 (2020)
Publication Year :
2024

Abstract

Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively leveraging 300mm fab processing. While the passivation of oxygen vacancies in IGZO is challenging with an integration of front side gate, a scaled back gated flow has been optimized by multiplying design of experiments around contacts and material engineering. We then successfully demonstrated sub-40mV $\sigma$(VTH_ON) in scaled IGZO nFETs. Regarding the performance and the VTH_ON control, a new IGZO phase is also reported. A model of dopants location is proposed to better explain the experimental results reported in literature.

Details

Database :
arXiv
Journal :
ECS Trans. 98 205 (2020)
Publication Type :
Report
Accession number :
edsarx.2411.16299
Document Type :
Working Paper
Full Text :
https://doi.org/10.1149/09807.0205ecst