Comparing different solutions for testing resistive defects in low-power SRAMs

Low-power SRAM architectures are especially sensitive to many types of defects that may occur during manufacturing. Among these, resistive defects can appear. This paper analyzes some types of such defects that may impair the device functionalities in subtle ways, depending on the defect characteristics, and that may not be directly or easily detectable by traditional test methods, such as March algorithms. We analyze different methods to test such defects and discuss them in terms of complexity and test time.
Comment: Paper accepted and presented in The 22nd IEEE Latin-American Test Symposium (LATS 2021) October 27 - 29, 2021, Brazil. It is going to be published in the IEEExplorer. 6 pages, 7 figures, 3 tables