Binary Addition in Resistance Switching Memory Array by Sensing Majority

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the &lsquo
von Neumann bottleneck&rsquo
or &lsquo
memory wall&rsquo
Emerging resistance switching memories (memristors) show promising signs to overcome the &lsquo
by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory R E A D operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory R E A D and W R I T E operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T&ndash
1R array, which is faster than I M P L Y , N A N D , N O R and other similar logic primitives.