Reducing Rad-Hard Memories for FPGA Configuration Storage on Space-bound Payloads

FPGA use in space-based applications is becoming more common. Radiation-hardened (rad-hard) memories are typically used to store configuration data for programming the FPGA and performing bitstream scrubbing to remove errors in the system that occur from single event upsets (SEUs). Since device densities for the latest FPGAs are growing at a faster rate than rad-hard memories, it is becoming more difficult to reliably store the FPGA configuration data without using a large number of memories. We present a method for cutting the use of rad-hard memories necessary to support the use of the latest FPGA technologies in space-based applications. This paper describes a solution to this memory problem which utilizes FPGA partial reconfiguration, with device self-scrubbing, and bitstream compression to create a minimally sized bootstrap design that has a memory footprint that is a fraction of the size of the original design. This bootstrap design is stored locally, and the remaining design elements can be reconfigured as necessary from a remote location. The resulting prototype design yields a compressed bitstream that at less than 2% the size of the bitstream for largest FPGA currently on the market.