Narrow-Band Receiver and Ultra-Wideband Low Noise Amplifier

In past years, the evolution in communication technology has led to a need forhighly-integrated, low-power, and low-cost circuit designs for wireless applications.The demand for radio frequency (RF) wireless transceiver operating at 2.4GHzband has attracted considerable research interest. The performance of suchtransceivers depends heavily on that of each of the individual blocks such as lownoiseamplifiers and mixers. However, there are very few designs that focus onconnecting the single-ended output low-noise amplifier (LNA) to a double-balancedmixer without the use of on-chip transformer. This kind of receiver front-end is designedto achieve high integration and low power consumption.In recent years, Ultra-Wideband (UWB) technology has developed very rapidlydue to its high data transmitting rate and low power consumption. Meanwhile, thedesign of an Ultra-Wideband low-noise amplifier (LNA) has become an importantchallenge since it is normally the front-end of the radio frequency (RF) receiver system.Low power consumption of an UWB LNA is a critical requirement for UWBapplication such as portable devices or especially in biomedical systems. However,the design should not only focus on low power, but also focus on optimizing otherperformances at competitive levels over the entire bandwidth, where the FederalCommunication Commission (FCC) has allocated 7.5 GHz of bandwidth from 3.1GHz to 10.6 GHz for Ultra-Wideband.This thesis focuses on the design of a fully-integrated RF receiver front-end includinga narrow-band LNA followed by a double balanced mixer. The receiver operates at 2.4 GHz and produces an output signal at 300 MHz. The circuit is designed and fabricated using TSMC O.lS-p,mCMOS technology. In order to translate the single-ended RF output signal from the LNA into the differential input pair of the mixer, a main novel idea of this design is to use one PMOS and one NMOS instead of two NMOS devices for the RF amplification stage of the double balanced mixer. The circuit achieves 16.3dB gain and 6.74mW power consumption while using 2.08 mm2 chip area.Another design presented in this thesis is a UWB LNA with special emphasizeon low power consumption as well as on optimizing the overall performance. Thecircuit is designed using TSMC 0.13-p,m CMOS technology. It achieves a very flatgain of 10.3-12.1 dB and 3.4-5.9 dB noise figure (NF) throughout the entire bandwidthof 3.1-10.6 GHz. The power consumption is 2.81 mWwhich is extremely low compared to other designs and the chip area is 0.48mm2 • The overall performance is also competitive according to its figure of merit (FoM). Master of Applied Science (MASc)