A digital ASIC for sub-ns timing with the LHCb RICH detectors in Run 4

This note complements the LHCb RICH Future Upgrades FTDR [1], which envisions possible evolutions of the LHCb RICH detectors in LHC Run 4 and Run 5. The addition of sub-ns time resolving capability to the LHCb RICH detectors is one of the key points, and would lead to reduced background, pile-up mitigation and ultimately improved PID. Examples of the improvement in signal over background rejection capabilities that can be obtained in Run 4 with the proposed system are described in [2]. This document describes the proposal to develop a fully digital, radiation hard ASIC to enable single photon counting with sub-ns resolution in the LHCb RICH detectors during Run 4. The proposed scheme is arguably the most cost-effective way to reach the goal of a RICH detector with sub-ns timing resolution, since it aims to make the best use of the timing capabilities of the LHCb RICH photodectors (MaPMTs) while reusing as much as possible the front-end electronics which have been installed for Run 3.