Through-polymer via (TPV) and method to manufacture such a via

The invention relates to vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers. In particular, the invention relates to a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers i.e. in an out-of-plane direction.