RTL Design Framework for Embedded Processor by using C++ Description

In this paper, we propose a method to directly describe the RTL structure of a pipelined RISC- V processor with cache, memory management unit (MMD) and AXI bus interface using C++ language. This processor C++ model serves as a near cycle-accurate simulation model of the RISC- V core, while our C2RTL framework translates the processor C++ model into cycle-accurate RTL description in Verilog-HDL and RTL-equivalent C model. Our design methodology is unique compared to other existing methodologies since both the simulation model and the RTL model are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor which runs Linux OS on an FPGA board as well as significantly short simulation time of the original C++ processor model and RTL-equivalent C model compared to commercial RTL simulator.