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AMMC: advance multi-core memory controller

Authors :
Oscar Palomar
S. A. Gursal
Mateo Valero
Eduard Ayguadé
Adrian Cristal
Tassadaq Hussain
Osman Unsal
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Barcelona Supercomputing Center
Source :
Recercat. Dipósit de la Recerca de Catalunya, Universitat Jaume I, FPT, UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
Publisher :
Institute of Electrical and Electronics Engineers (IEEE)

Abstract

In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC system improves performance by managing complex data transfers at run-time and scheduling multi-cores without the intervention of a control processor nor an operating system. AMMC has been coupled with a heterogeneous system that provides both general-purpose cores and application specific accelerators. The AMMC system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the AMMC based multi-core system consumes 48% less hardware resources, 27.9% less on-chip power and achieves 6.8x of speed-up compared to the MicroBlaze-based multi-core system.

Details

Database :
OpenAIRE
Journal :
Recercat. Dipósit de la Recerca de Catalunya, Universitat Jaume I, FPT, UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
Accession number :
edsair.doi.dedup.....d9cd17da27d75acd9139b360cd1099eb