MRL Crossbar-Based Full Adder Design

Memristor technology has acquired great interest in the field of non-volatile memories as well as logic computation. The nano-scale structure of memristor and the possibility of its integration with MOSFETs have triggered many efforts to reconstruct basic digital building blocks. Recently, Memristor Ratioed Logic (MRL) has been introduced as a hybrid memristor-CMOS logic design style, which has been functionally validated. In this paper, a 1-bit full adder is designed by implementing MRL in crossbar array. The new design methodology efficiently integrates memristors at the top of CMOS layer. The corresponding layout and simulation results are performed using Cadence Virtuoso toolset targeting CMOS 65 nm process. The obtained results and their corresponding comparison illustrate promising outcomes in terms of implementation area, energy consumption and speed.