Back to Search Start Over

Power efficient data cache designs

Authors :
Antonio González
Jaume Abella
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
Source :
Recercat. Dipósit de la Recerca de Catalunya, instname, ICCD, Scopus-Elsevier, UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
Publisher :
Institute of Electrical and Electronics Engineers (IEEE)

Abstract

We investigate some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different threshold voltages with different cache organizations that provide different levels of performance. Multibanked organizations in combination with different approaches to allocate data to cache banks are explored. Some of the resulting cache architectures are shown to provide a good tradeoff between power and performance.

Details

Database :
OpenAIRE
Journal :
Recercat. Dipósit de la Recerca de Catalunya, instname, ICCD, Scopus-Elsevier, UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
Accession number :
edsair.doi.dedup.....d4ad7ef47bb2a8b586f31950f375c28f