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Scale up your in-memory accelerator: leveraging wireless-on-chip communication for aimc-based cnn inference
- Source :
- 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
- Publication Year :
- 2022
-
Abstract
- Analog In-Memory Computing (AIMC) is emerging as a disruptive paradigm for heterogeneous computing, potentially delivering orders of magnitude better peak performance and efficiency over traditional digital signal processing architectures on Matrix-Vector multiplication. However, to sustain this throughput in real-world applications, AIMC tiles must be supplied with data at very high bandwidth and low latency; this poses an unprecedented pressure on the on-chip communication infrastructure, which becomes the system's performance and efficiency bottleneck. In this context, the performance and plasticity of emerging on-chip wireless communication paradigms provide the required breakthrough to up-scale on-chip communication in large AIMC devices. This work presents a many-tile AIMC architecture with inter-tile wireless communication that integrates multiple heterogeneous computing clusters, embedding a mix of parallel RISC-V cores and AIMC tiles. We perform an extensive design space exploration of the proposed architecture and discuss the benefits of exploiting emerging on-chip communication technologies such as wireless transceivers in the millimeter-wave and terahertz bands. This work was supported by the WiPLASH project (g.a. 863337), founded from the European Union’s Horizon 2020 research and innovation program.
- Subjects :
- FOS: Computer and information sciences
In-memory computing
Xarxes en xip
Scale-up
Millimeter waves
Systems and Control (eess.SY)
Efficiency
Radio transceivers
Ordinadors immersos, Sistemes d'
Electrical Engineering and Systems Science - Systems and Control
Wireless-based communications
Hardware Architecture (cs.AR)
FOS: Electrical engineering, electronic engineering, information engineering
Peak performance
Computer Science - Hardware Architecture
Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC]
Parallel processing (Electronic computers)
Processament en paral·lel (Ordinadors)
Terahertz waves
Network architecture
On chip communication
Digital signal processing
Embedded computer systems
Heterogeneous systems
Network-on-chip
Orders of magnitude
In-Memory Computing, Heterogeneous Systems, Network-on-Chip, Wireless-based Communications
Networks on a chip
Heterogeneous computing
Memory architecture
Subjects
Details
- ISBN :
- 978-1-66540-996-4
- ISBNs :
- 9781665409964
- Database :
- OpenAIRE
- Journal :
- 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)
- Accession number :
- edsair.doi.dedup.....d1deb71343d11cec36fdaf884a11d4e0
- Full Text :
- https://doi.org/10.1109/aicas54282.2022.9869996