Techniques to enhance the reliability of delay-based physical unclonable functions

Semiconductor device manufacturing has seen a constant decrease in transistors gate dimensions over the course of the last six decades, which also led to an increased influence of slight variations like random dopant variations and varying oxide thickness from manufacturing the physical instances. In the design of microelectronic chips, device mismatch usually degrades the performance of a system and thus is minimized as far as possible by design techniques or auxiliary systems within a chip. Physical Unclonable Functions are a promising alternative to storing secure encryption keys in non-volatile memory and utilize device mismatch as a source of unpredictable but static information contained in the physics of an integrated circuit itself. Physical Unclonable Functions have raised interest especially in the field of low-power IoT devices due to their small size, low costs, low power requirements and intrinsic resilience against physical tampering. In this thesis, techniques to enhance delay based Physical Unclonable Functions in the analog and the digital domain are investigated and analyzed. Arbiter PUFs are improved by a two-fold approach: First, custom sizing of transistors is investigated with respect to scaling effects on the ratio between mismatch and electrical noise in order to increase the reproducibility of measurement readouts. Second, a redesign of the measurement circuitry is investigated where the arbitration circuitry is extended to also function as a deadzone detector. This approach is complemented by feedback repetitive measurements, similar to oscillators, in order to avoid readouts with a minor phase difference, which would be strongly affected by electrical noise. Ring oscillators on FPGAs are investigated regarding their reproducibility and their individual bias based on their location on the chip. Counter failures occurring in high frequency oscillations are strongly reduced by a combination of an improved counter design, reference normalization and an additional feedback path of the ring oscillator for glitch avoidance. Analysis of the areal mismatch distribution is carried out to identify systematic and thus predictable bias.