(Invited) Floating Gate Type SOI-FinFET Flash Memories with Different Channel Shapes and Interpoly Dielectric Materials

It is well known that the high-k interpoly dielectric (IPD) layer is important for further scaling down of floating gate (FG) type flash memory to improve the gate coupling ratio [1, 2]. Therefore, the high-k Al2O3 layer has already been used as a blocking layer in the charge trapping (CT) type planar and bulk FinFET flash memories [3-5]. However, the high-k Al2O3 has not been used as an IPD layer in the FG type SOI-FinFET flash memories, to our knowledge. In this work, we introduce the high-k Al2O3 into the FG type triangular-fin (TF) and rectangular-fin (RF) channel SOI-FinFET flash memories, and investigate the effects of fin shape and IPD layer material on the electrical characteristics of the fabricated FG type SOI-FinFET flash memories. In the device fabrication, we used (100) and (110) oriented SOI wafers to fabricate TF and RF channels by using the orientation dependent wet etching [6]. A 30-nm-thick n+ poly-Si layer was used as the FG material. Figure 1 shows the cross-sectional STEM images of the fabricated FG-type SOI-FinFET flash memories with different channel shapes and different IPD layers. Figure 2 shows the P/E characteristics of the fabricated 3 kinds of SOI-FinFET flash memories at the same P/E condition. It is clear that a higher P/E speed, a larger memory window and a lower-voltage operation are achieved in the TF-ONA device as compared to the TF-ONO and RF-ONA ones. This result indicates that a high-k Al2O3 layer is very useful for enhancing memory window due to the improved gate coupling, and the TF channel is very suitable for the low-voltage operation thanks to the high-k of Al2O3 and the electric field enhancement at the sharp foot edges of a TF. [1] B. Govoreanu et al., IEDM 2006, p. 479. [2] H.-T. Lue et al., IEDM 2011, p. 203. [3] C. H. Lee et al., IEDM 2003, p. 613. [4] S.-K. Sung et al., VLSI 2006, p.106. [5] B. J. Tang et al., IEDM 2011, p. 219. [6] Y. X. Liu et al., VLSI 2010, p.101. Figure 1