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Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip
- Source :
- Scopus-Elsevier
- Publication Year :
- 2000
- Publisher :
- IOP Publishing, 2000.
-
Abstract
- A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.
- Subjects :
- Packaging engineering
Computer science
business.industry
General Engineering
Stacking
General Physics and Astronomy
Hardware_PERFORMANCEANDRELIABILITY
Chip
Vertical direction
Hardware_INTEGRATEDCIRCUITS
Key (cryptography)
Development (differential geometry)
Wafer
Image sensor
business
Computer hardware
Subjects
Details
- ISSN :
- 13474065 and 00214922
- Volume :
- 39
- Database :
- OpenAIRE
- Journal :
- Japanese Journal of Applied Physics
- Accession number :
- edsair.doi.dedup.....aa6a573db6a7cb0dadf16937961a2aab