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A RISC-V ISA extension for ultra-low power IoT wireless signal processing
- Source :
- IEEE Transactions on Computers, IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2021, 2021, pp.1-1. ⟨10.1109/TC.2021.3063027⟩, IEEE Transactions on Computers, 2021, 2021, pp.1-1. ⟨10.1109/TC.2021.3063027⟩, IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2021, pp.1-1. ⟨10.1109/TC.2021.3063027⟩
- Publication Year :
- 2021
- Publisher :
- HAL CCSD, 2021.
-
Abstract
- International audience; This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to come at a near-zero energy cost. Both an instruction accurate (IA) and a cycle accurate (CA) model of the new architecture are used to evaluate six IoT baseband processing test benches including FSK demodulation and LoRa preamble detection. Simulation results show cycle count improvements from 19% to 68%. Post synthesis simulations for a target 22nm FD-SOI technology show less than 1% power and 28% area overheads, respectively, relative to a baseline RV32IM design. Power simulations show a peak power consumption of 380 µW for Bluetooth LE demodulation and 225 µW for LoRa preamble detection (BW = 500 kHz, SF = 11).
- Subjects :
- IoT
Computer science
02 engineering and technology
LoRa
Theoretical Computer Science
law.invention
Bluetooth
[SPI]Engineering Sciences [physics]
law
0202 electrical engineering, electronic engineering, information engineering
Demodulation
Wireless
software-defined radio
Frequency-shift keying
business.industry
Software-defined radio
020202 computer hardware & architecture
Computational Theory and Mathematics
Hardware and Architecture
RISC-V
Baseband
Transceiver
business
ISA extension
Software
Computer hardware
ultra-low power (ULP) transceiver architecture
Subjects
Details
- Language :
- English
- ISSN :
- 00189340
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computers, IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2021, 2021, pp.1-1. ⟨10.1109/TC.2021.3063027⟩, IEEE Transactions on Computers, 2021, 2021, pp.1-1. ⟨10.1109/TC.2021.3063027⟩, IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2021, pp.1-1. ⟨10.1109/TC.2021.3063027⟩
- Accession number :
- edsair.doi.dedup.....a3d65f6b50d4bc6212a1b2e16f520569