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Design and implementation of a fast digital fuzzy logic controller using FPGA technology
- Publication Year :
- 2006
-
Abstract
- Fuzzy logic controllers (FLCs) are finding increasing popularity in real industrial applications, especially when the available system models are inexact or unavailable. This paper proposes a zero-order Takagi---Sugeno parameterized digital FLC, processing only the active rules (rules that give a non-null contribution for a given input data set), at high frequency of operation, without significant increase in hardware complexity. To achieve this goal, an improved method of designing the fuzzy controller model is proposed that significantly reduces the time required to process the active rules and effectively increases the input data processing rate. The digital fuzzy logic controller discussed in this paper achieves an internal core processing speed of at least 200 MHz, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape membership functions per input and a rule base of up to 49 rules. The proposed architecture was implemented in a field programmable gate array chip with the use of a very high-speed integrated-circuits hardware description language and advanced synthesis and place and route tools.
- Subjects :
- Very high-speed hardware description language
Computer science
Digital fuzzy logic controller
Fuzzy logic
Industrial and Manufacturing Engineering
Synthesis
Artificial Intelligence
Control theory
Place and route
Electrical and Electronic Engineering
Field-programmable gate array
Register-transfer level
computer.programming_language
Data processing
business.industry
Mechanical Engineering
Hardware description language
Control engineering
Register transfer level
Electrical Engineering - Electronic Engineering - Information Engineering
Odd–even method
Fuzzy electronics
Control and Systems Engineering
Engineering and Technology
business
computer
Software
Computer hardware
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Accession number :
- edsair.doi.dedup.....a27f9d4d9402a2d8cbc7b144787052d4