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Prototyping dynamic task migration on heterogeneous reconfigurable systems
- Source :
- International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, Oct 2017, Seoul, South Korea, 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype (RSP 2017), 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype (RSP 2017), Oct 2017, Seoul, North Korea. pp.16-22, RSP
- Publication Year :
- 2017
- Publisher :
- HAL CCSD, 2017.
-
Abstract
- International audience; Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions.In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented.
- Subjects :
- [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
[INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR]
Coprocessor
Computer science
task
02 engineering and technology
Dynamic priority scheduling
migration
01 natural sciences
Task (project management)
task-specific
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Hardware_ARITHMETICANDLOGICSTRUCTURES
Field-programmable gate array
FPGA
ComputingMilieux_MISCELLANEOUS
010302 applied physics
business.industry
Context (computing)
Context management
020202 computer hardware & architecture
Embedded system
Hetegeneous
PACS 85.42
Task analysis
Benchmark (computing)
business
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Journal :
- International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, Oct 2017, Seoul, South Korea, 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype (RSP 2017), 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype (RSP 2017), Oct 2017, Seoul, North Korea. pp.16-22, RSP
- Accession number :
- edsair.doi.dedup.....8843eeb40f9c686f69788dac64622cc5