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RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures

Authors :
Francesco Conti
Luca Benini
Gianna Paulin
Renzo Andri
Paulin G.
Andri R.
Conti F.
Benini L.
Source :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:1624-1637
Publication Year :
2021
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2021.

Abstract

Radio resource management (RRM) is critical in 5G mobile communications due to its ubiquity on every radio device and its low latency constraints. The rapidly evolving RRM algorithms with low latency requirements combined with the dense and massive 5G base station deployment ask for an on-the-edge RRM acceleration system with a tradeoff between flexibility, efficiency, and cost-making application-specific instruction-set processors (ASIPs) an optimal choice. In this work, we start from a baseline, simple RISC-V core and introduce instruction extensions coupled with software optimizations for maximizing the throughput of a selected set of recently proposed RRM algorithms based on models using multilayer perceptrons (MLPs) and recurrent neural networks (RNNs). Furthermore, we scale from a single-ASIP to a multi-ASIP acceleration system to further improve RRM throughput. For the single-ASIP system, we demonstrate an energy efficiency of 218 GMAC/s/W and a throughput of 566 MMAC/s corresponding to an improvement of $10\times $ and $10.6\times $ , respectively, over the single-core system with a baseline RV32IMC core. For the multi-ASIP system, we analyze the parallel speedup dependency on the input and output feature map (FM) size for fully connected and LSTM layers, achieving up to $10.2\times $ speedup with 16 cores over a single extended RI5CY core for single LSTM layers and a speedup of $13.8\times $ for a single fully connected layer. On the full RRM benchmark suite, we achieve an average overall speedup of $16.4\times $ , $25.2\times $ , $31.9\times $ , and $38.8\times $ on two, four, eight, and 16 cores, respectively, compared to our single-core RV32IMC baseline implementation.

Details

ISSN :
15579999 and 10638210
Volume :
29
Database :
OpenAIRE
Journal :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accession number :
edsair.doi.dedup.....6d32647f1a99cce970fe640197e46e9e